Designing for excellent signal integrity starts with a pre-layout analysis. This can begin after component placement and a first pass stackup is available from our PCB Partner.
The pre-layout analysis is a full 3D simulation of all the channel transitions for a given set of nets, typically shortest and longest combined with other worst case conditions. The frequency domain results are compared to industry masks/guidelines for insertion loss, differential and common mode return loss, mode conversion and crosstalk. IBIS-AMI simulations can be done if models are available, stable and accurate. If a mask failure is present, iterations are done on the variables that can be changed in the design. Examples could be layer escape, drilling methods, antipad size, drill size, pcb material, connector style etc.
When a solution is found, CAD Guidelines are then generated to show the PCB designer exactly what is needed to execute the routing successfully for each interface.
When routing is complete, all changes from pre-layout are included in another round of 3D modeling and channel simulations. This is considered “post-layout” analysis. Both frequency domain mask comparisons and statistical eye diagrams are generated, if applicable. Some standards bodies are providing their own methods for generating statistical eye results based on adaptive DFE and Tx pre and post cursor settings (Examples are PCIe Gen 3, IEEE 802.3bj, SAS 2.0).
Arira Design specializes in simulation of high-speed interconnects. We are focused on signal integrity consulting with particular expertise in converging on manufacturable solutions to SI problems. We use a suite of leading-edge simulation tools from Ansys such as HFSS, Designer-SI, and Q3D to create frequency and time-domain simulations of high-speed differential pair and memory designs.
Arira’s experience includes DDR2 and DDR3 Memory, HMC Memory, SAS, SATA, SRIO, PCIe, HDMI, Gigabit Ethernet, Fibre Channel, and Infiniband, at speeds from 400Mbps up to 30Gbps.
Case Studies of Signal Integrity
For a recent DXAUI design, a challenging issue was the resonant frequency of the AirMax connector at 4GHz, the large drill size driving the impedance of the launch down and the skew inside the connector. We swapped the P and N signals on the backplane, which eliminated the skew and resultant mode conversion. We ended up with 35dB of signal to noise margin at 3.125GHz. For PCIe Gen 2 we used the same guidelines we generated for DXAUI.For the SFI interface, we used a via-in-pad approach for all the layer transitions. We electromagnetically tuned the SFP and BGA interfaces for lowest possible return loss (16-18 dB at 5GHz). The result was ILD with +/- 0.1dB and wide open eyes simulated with Broadcom’s LinkEye tool.
For the DDR3 interface, the challenge was understanding the termination scheme on the 4 devices that were part of the DQ net. After many simulations and unsatisfactory results, we iterated with Virtium to get the proper termination arrangement, and the DQ and DQS nets started came together nicely in the end.
SI Tools Used:
- Software Resources
- Agilent ADS
- Statistical Eye simulation using IBIS-AMI Models
- Agilent ADS
- Ansoft HFSS
- 3D Modeling of PCB structures
- In-house automation ensures faster response and consistency
- Apsim RLGC
- 2D Modeling of PCB Transmission Lines
- Frequency-dependant W-elements
- Time Domain Simulation using IBIS and AMI.
- Frequency Domain Simulation
- Concatenation of S-Parameters